This invention generally relates to an embedded dynamic random access memory and, more particularly, to a gain cell attached to a deep trench capacitor to enable long retention time and soft error immunity for system-on-chip applications.
Typically, semiconductor memories use six transistor static memory (6T SRAM) cells or one transistor dynamic random access memory (1T DRAM) cells. FIG. 1A shows a transistor level schematic of a typical 6T SRAM cell 0 consisting of four NMOS transistors 1, 2, 5 and 6, and two PMOS transistors 3 and 4. PMOSs 3 and 4 and NMOSs 5 and 6 are linked to each other to structure a CMOS cross-coupled latch that forms a storage element for storing a data bit. NMOSs 1 and 2 respectively couple nodes (also referred to terminals) 7 and 8 to biltlines BL and bBL when a wordline WL is activated, allowing reading or writing a data bit from the bit lines BL and bBL. When the memory is in write mode, BL or bBL switches to low depending on the write data bit. This allows flipping the CMOS cross-coupled latch to overwrite the data bit in the 6T SRAM cell 0. The overwritten data bit in the cell is maintained by the CMOS cross-coupled latch after the write operation (non-destructive write). When the memory structure is in read mode, either BL or bBL is directly driven by the CMOS cross-coupled latch. The self-gain feature of the 6T SRAM cell results in a fast read access speed. The read operation does not affect the data bit in the CMOS cross-coupled latch. The 6T SRAM cell maintains the data bit after the read operation (non-destructive read). The non-destructive write and non-destructive read features for the 6T SRAM cell achieve a fast random read and write cycle times. However, the 6T SRAM cell requires six transistors, p-type and n-type well isolation, and cross-coupled wiring, resulting in a cell six to ten times larger than a 1T DRAM cell.
FIG. 1B is a transistor level schematic representation of a 1T DRAM cell 10. It consists of one NMOS transistor 11 and a capacitor 12 (1T DRAM cell). Typically, capacitor 12 may be structured as a trench, planar or stack capacitor. When wordline WL is activated, NMOS 11 links capacitor 12 to bitline BL. The charge sharing effect between capacitor 12 and BL creates a small BL voltage. This charge sharing destroys the data bit in capacitor 12 (destructive read). The small BL voltage is sensed by a sense amplifier (not shown) coupled to BL, resulting in a slower access speed than of a 6T SRAM cell. The sense amplifier drives BL depending on the outcome of the sensing operation, rewriting the read data bit in capacitor 12 (write back). When the memory is in write mode, BL is driven either low or high, depending on the data pattern. Typically, the write mode operation is enabled after a read mode operation because only selected cells remain in the write mode, the remaining cell data bits having been destroyed when activating WL (destructive write). Accordingly, the destroyed data bits need to be rewritten by the sense amplifier simultaneously with the write data bits (read modified write). The destructive read followed by the write back and the read modified write caused by the destructive write require a longer cycle time than that of a typical 6T SRAM cell. However, a 1T DRAM cell requires only one transistor and one capacitor, resulting in a cell which is one-sixth to one-tenth smaller than a 6T SRAM cell.
FIG. 2A is a transistor level schematic representation of a 3T-gain cell. During write mode, the write wordline WWL switches to high, making it possible to couple storage node 24 to write bitline WBL through NMOS transistor 23. This operation is similar to the write operation for the previously described 1T DRAM cell. During read mode, the read wordline RWL switches to high, reading out the data to read bitline RBL through the series arrangement of NMOS transistors 21 and 22. When storage node (or terminal) 24 maintains the data at high, the two NMOS transistors 21 and 22 are both on, discharging RBL. When the storage node is held at a low voltage, NMOS transistor 22 remains off which, in turn, keeps RBL at a precharged voltage. Depending on the data pattern, RBL is directly driven by the series of NMOS transistors 21 and 22. This self-gain feature results in a fast read access speed similar to the 6T SRAM cell. The read operation does not affect the data bit present in storage node 24. The 3T-gain cell holds the data bit even after the read operation (non-destructive read out), producing a fast random read access cycle. The 3T-gain cell requires three transistors, without necessitating p-type and n-type well isolation and cross-coupled wiring, and creates a cell three times smaller than a 6T SRAM cell.
FIG. 2B is a schematic of a transistor level representation of a 2T-gain cell. Unlike the 3T-gain cell, the read NMOS switching transistor 21 is altogether eliminated. During write mode, write wordline WWL switches to high, coupling storage node 27 to write bitline WBL through NMOS transistor 26. This operation is similar to a write operation for the 1T DRAM cell. The source and drain of NMOS transistor 25 are respectively coupled to the read wordline RWL and read bitline RBL. Moreover, when in standby mode, RWL and RBL are precharged to supply voltage VDD. During read mode, the read wordline RWL switches to low. If the data bit in storage node 27 is at low, NMOS 25 remains off, leaving RBL at high. When the data bit is at high, NMOS 25 remains on, forcing RBL to switch to low. Note that RBL is driven directly by RWL. This self-gain feature results in a fast read access speed, similar to the 6T SRAM cell. The read operation does not affect the data bit in storage node 27. The 2T SRAM cell holds the data bit even after the read operation (non-destructive read), thus enabling a fast read random cycle time. The 2T gain cell requires only two transistors without requiring a p-type and n-type well isolation, and/or cross-coupled wiring, all of which results in a cell four times smaller than the size of a 6T SRAM cell.
Generally both the 3T and 2T-gain cells achieve a fast read access and significantly improved cycle times. However, as the storage node 24 or 27 voltage decreases, the self-gain is, likewise, also reduced. Furthermore, as the size of the 3T and 2T gain cells shrinks, the gate capacitor of NMOS transistor 22 or 25 also decreases, resulting in a potential performance and data retention degradation as well as a poor soft error rate.
Accordingly, it is an object of the present invention to provide a 2T and 3T-gain cell integrated with a deep trench capacitor.
It is another object of the present invention to improve the data retention by integrating a gain cell integrated with a deep trench capacitor.
It is a further object of the present invention to construct a gain cell structure having an outstanding error immunity.
In a first aspect of the invention, there is described a gain cell structure and an array configuration applicable to trench technology. The 3T and 2T gain cells include a trench capacitor in the storage node such that the storage voltage is maintained for a long retention time. The gate of the gain transistor and the trench capacitor are placed alongside the read and write wordline. This arrangement makes it possible to have the gain transistor directly coupled to the trench capacitor, resulting in a smaller cell size.
In a second aspect of the invention there is provided a memory cell that includes a first transistor provided with a gate, a source, and a drain respectively coupled to a read wordline, a first node, and a read bitline; a second transistor having a gate, a source, and a drain respectively coupled to a storage node, to a voltage source, and to the first node; a third transistor having a gate, a source, and a drain respectively coupled to a write wordline, the storage node, and a write bitline; and a capacitor having a first terminal connected to the storage node and a second terminal connected to a voltage source.
In a second aspect of the invention there is provided a memory cell that includes: a first transistor having a gate, a source, and a drain respectively coupled to a storage node, a read wordline, and a read bitline; a second transistor having a gate, a source, and a drain respectively coupled to a write wordline, a write bitline, and the storage node; and a capacitor having a first terminal connected to the storage node and a second terminal connected to a voltage source.